Conventionally, there is a known semiconductor device that includes a semiconductor chip mounted on a chip mounting region of a wiring board. The wiring board and the semiconductor chip are electrically connected via solder bumps respectively formed on the wiring board and the semiconductor chip. As an example, Japanese Laid-Open Patent Publication No. 2004-253544 proposes arranging the solder bumps of the wiring board to oppose the corresponding solder bumps of the semiconductor chip, and melting and thereafter coagulating the solder bumps, to cause alloying of the solder bumps and achieve the electrical connection.
However, when the chip mounting region of the wiring board is warped, a distance between the solder bump of the wiring board and the corresponding solder bump of the semiconductor chip varies depending on the position within the chip mounting region. For this reason, at the position within the chip mounting region, where the distance between the corresponding solder bumps is short, adjacent solder bumps may become connected by the excessive amount of solder. In this first case, there is a high possibility that a solder bridge connecting the adjacent solder bumps will generate a short-circuit. On the other hand, at the position within the chip mounting region, where the distance between the corresponding solder bumps is long, the corresponding solder bumps may not become connected due to insufficient amount of solder. In this latter case, there is a high possibility that the non-connecting, corresponding solder bumps will generate an open-circuit. In other words, because the distance between the solder bump of the wiring board and the corresponding solder bump of the semiconductor chip varies depending on the position within the chip mounting region, a reliability of the connection between the wiring board and the semiconductor chip deteriorates.